PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
8.1 INTCON Registers
The INTCON Registers are readable and writable reg-
isters, which contain various enable, priority and flag
bits.
REGISTER 8-1:
INTCON REGISTER
R/W-0
R/W-0
R/W-0
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
R/W-0
INT0IE
R/W-0 R/W-0 R/W-0
RBIE TMR0IF INT0IF
R/W-x
RBIF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all interrupts
0 = Disables all interrupts
bit 6
PEIE/GEIL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB5:RB0 pins changed state (must be cleared in software)
0 = None of the RB5:RB0 pins have changed state
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR Reset ’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 61
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