PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC18F010T-I/SN' PDF : 176 Pages View PDF
5.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>), and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore, it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
EXAMPLE 5-1: DATA EEPROM READ
MOVLW DATA_EE_ADDR ;
MOVWF EEADR
;Data Memory Address to read
BCF EECON1, EEPGD ;Point to DATA memory
BSF EECON1, RD ;EEPROM Read
MOVF EEDATA, W
;W = EEDATA
5.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then the sequence in
Example 5-2 must be followed to initiate the write cycle.
Note: Do not write to program memory or
EECON1 while writing to EEDATA.
PIC18F010/020
EXAMPLE 5-2: DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
DATA_EE_ADDR ;
EEADR
; Data Memory
Address to write
DATA_EE_DATA ;
EEDATA
; Data Memory
Value to write
EECON1, EEPGD ; Point to DATA
memory
EECON1, WREN ; Enable writes
BCF INTCON, GIE
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
AAh
EECON2
EECON1, WR
BSF INTCON, GIE
; Disable
Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to
begin write
; Enable
Interrupts
SLEEP
BCF
EECON1, WREN
; Wait for
interrupt to
signal write
complete
; Disable writes
The write will not initiate if the above required sequence
is not exactly followed (write 55h to EECON2, write
AAh to EECON2, then set WR bit) for each byte. It is
strongly recommended that interrupts be disabled dur-
ing this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 45
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