PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I/SN' PDF : 176 Pages View PDF
PIC18F010/020
5.5 Protection Against Spurious Write
5.5.1 EEPROM DATA MEMORY
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
5.6 Operation During Code Protect
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
5.6.1 DATA EEPROM MEMORY
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
TABLE 5-1: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Address Name Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
FA9h
EEADR EEPROM Address Register
FA8h
EEDATA EEPROM Data Register
FA7h
EECON2 EEPROM Control Register2 (not a physical register)
FA6h
EECON1 EEPGD
—
— FREE WRERR WREN WR
FA2h
IPR2
—
—
—
EEIP
—
LVDIP —
FA1h
PIR2
—
—
—
EEIF
—
LVDIF —
FA0h
PIE2
—
—
—
EEIE
—
LVDIE —
FF2h
INTCON GIE/GIEH PEIE/GIEL T0IE INT0IE RBIE T0IF INT0F
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- ---- ---- ----
RD x--0 x000 u--0 u000
— ---1 1--- ---1 1---
— ---0 0--- ---0 0---
— ---0 0--- ---0 0---
RBIF 0000 000x 0000 000u
DS41142A-page 46
Preliminary
2001 Microchip Technology Inc.
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