PIC18F010/020
REGISTER 8-6:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER2 (FA2h)
U-0
U-0
U-0
R/W-1
U-0
R/W-1
U-0
—
—
—
EEIP
—
LVDIP
—
bit 7
U-0
—
bit 0
bit 7-5
bit 4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
EEIP: EEPROM Write Timer Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
LVDIP: Low Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 65