PIC18F010T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I/SO' PDF : 176 Pages View PDF
PIC18F010/020
8.5.1 INT0 INTERRUPT
The external interrupt on the RB2/INT0 pin is edge trig-
gered: either rising if the INTEDG0 bit is set in the
INTCON2 register, or falling if the INTEDG0 bit is clear.
When a valid edge appears on the RB0/INT0 pin, the
flag bit INT0F is set. Clearing the enable bit INT0E will
disable this interrupt. Flag bit INT0F must be cleared in
software in the Interrupt Service Routine before re-
enabling the interrupt. The external interrupt can wake-
up the processor from SLEEP. If the global interrupt
enable bit GIE is set, the processor will branch to the
interrupt vector following wake-up.
Note:
There is no priority bit associated with
INT0. It is always a high priority interrupt
source.
8.5.2 TMR0 INTERRUPT
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See Sec-
tion 8.0 for further details on the Timer0 module.
8.5.3 PORTB INTERRUPT-ON-CHANGE
An interrupt change on any pin in PORTB sets flag bit
RBIF in INTCON. The interrupt can be enabled/dis-
abled by setting clearing the enable bit RBIE in
INTCON. The bit RBIP in INTCON2 determines the pri-
ority of the interrupt.
Each of the PORTB pins is individually configurable as
an interrupt-on-change pin. Control bits IOCBx in the
IOCB register, Register 9-2, enable or disable the inter-
rupt function for each pin. The interrupt-on-change is
disabled on a Power-on Reset.
8.6 Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved. Example 6-1
saves and restores the WREG, STATUS and BSR
registers during an Interrupt Service Routine.
EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP
MOVFF STATUS, STATUS_TEMP
MOVFF BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR
MOVF W_TEMP, W
MOVFF STATUS_TEMP, STATUS
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
DS41142A-page 66
Preliminary
2001 Microchip Technology Inc.
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