PIC18F6310 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F6310' PDF : 404 Pages View PDF
PIC18F6310/6410/8310/8410
TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 57, 64
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 57, 64
TOSL
STKPTR
Top-of-Stack Low Byte (TOS<7:0>)
STKFUL(6) STKUNF(6)
—
Return Stack Pointer
0000 0000 57, 64
00-0 0000 57, 65
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000 57, 64
PCLATH
Holding Register for PC<15:8>
0000 0000 57, 64
PCL
PC Low Byte (PC<7:0>)
0000 0000 57, 64
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 57, 88
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 57, 88
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 57, 88
TABLAT
Program Memory Table Latch
0000 0000 57, 88
PRODH
Product Register High Byte
xxxx xxxx 57, 99
PRODL
Product Register Low Byte
xxxx xxxx 57, 99
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 57, 103
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP 1111 1111 57, 104
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF 1100 0000 57, 105
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
57, 79
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
57, 80
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
57, 80
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
57, 80
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register),
value of FSR0 offset by W
N/A
57, 80
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx 57, 79
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 57, 79
WREG
Working Register
xxxx xxxx 57
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
57, 79
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
57, 80
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
57, 80
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
57, 80
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register),
value of FSR1 offset by W
N/A
57, 80
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- xxxx 57, 79
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 57, 79
BSR
—
—
—
—
Bank Select Register
---- 0000 57, 69
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
58, 79
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
58, 80
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
58, 80
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
58, 80
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register),
value of FSR2 offset by W
N/A
58, 80
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- xxxx 58, 79
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 58, 79
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 58, 77
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 73
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