PIC18F6310 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F6310' PDF : 404 Pages View PDF
PIC18F6310/6410/8310/8410
TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRGH1 EUSART1 Baud Rate Generator High Byte
0000 0000 60, 213
BAUDCON1 ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN 01-0 0-00 60, 212
SPBRG2 AUSART2 Baud Rate Generator
0000 0000 60, 234
RCREG2 AUSART2 Receive Register
0000 0000 60, 238
TXREG2 AUSART2 Transmit Register
xxxx xxxx 60, 236
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 60, 232
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 60, 233
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
DS39635A-page 76
Preliminary
2004 Microchip Technology Inc.
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