PIC18F6310 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F6310' PDF : 404 Pages View PDF
PIC18F6310/6410/8310/8410
TABLE 5-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRG1 EUSART1 Baud Rate Generator
0000 0000 59, 213
RCREG1 EUSART1 Receive Register
0000 0000 59, 220
TXREG1 EUSART1 Transmit Register
xxxx xxxx 59, 218
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D xxxx xxxx 59, 210
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 0000 59, 211
IPR3
—
—
RC2IP
TX2IP
—
—
—
CCP3IP --00 ---1 59, 114
PIR3
—
—
RC2IF
TX2IF
—
—
—
CCP3IF --00 ---1 59, 108
PIE3
—
—
RC2IE
TX2IE
—
—
—
CCP3IE --00 ---1 59, 111
IPR2
OSCFIP
CMIP
—
—
BCLIP
HLVDIP
TMR3IP
CCP2IP 11-- 1111 59, 113
PIR2
OSCFIF
CMIF
—
—
BCLIF
HLVDIF
TMR3IF
CCP2IF 00-- 0000 59, 107
PIE2
OSCFIE
CMIE
—
—
BCLIE
HLVDIE
TMR3IE
CCP2IE 00-- 0000 59, 110
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP 1111 1111 59, 112
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 59, 106
PIE1
MEMCON(2)
OSCTUNE
TRISJ(2)
TRISH(2)
PSPIE
ADIE
RC1IE
EBDIS
INTSRC
—
PLLEN(3)
WAIT1
—
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
TX1IE
WAIT0
TUN4
SSPIE
—
TUN3
CCP1IE
—
TUN2
TMR2IE
WM1
TUN1
TMR1IE
WM0
TUN0
0000 0000
0-00 --00
00-0 0000
1111 1111
1111 1111
59, 109
59, 89
33, 59
59, 139
59, 137
TRISG
—
—
—
Data Direction Control Register for PORTG
---1 1111 60, 135
TRISF
Data Direction Control Register for PORTF
1111 1111 60, 133
TRISE
Data Direction Control Register for PORTE
1111 1111 60, 131
TRISD
Data Direction Control Register for PORTD
1111 1111 60, 128
TRISC
Data Direction Control Register for PORTC
1111 1111 60, 125
TRISB
TRISA
LATJ(2)
LATH(2)
Data Direction Control Register for PORTB
TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
60, 122
60, 119
60, 139
60, 137
LATG
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
---x xxxx 60, 135
LATF
Read PORTF Data Latch, Write PORTF Data Latch
xxxx xxxx 60, 133
LATE
Read PORTE Data Latch, Write PORTE Data Latch
xxxx xxxx 60, 131
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx 60, 128
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx 60, 125
LATB
LATA
PORTJ(2)
PORTH(2)
PORTG
Read PORTB Data Latch, Write PORTB Data Latch
LATA7(5) LATA6(5) Read PORTA Data Latch, Write PORTA Data Latch
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
—
—
RG5(4) Read PORTG pins <4:0>, Write PORTG Data Latch <4:0>
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
60, 122
60, 119
60, 139
60, 137
60, 135
PORTF
Read PORTF pins, Write PORTF Data Latch
xxxx xxxx 60, 133
PORTE
Read PORTE pins, Write PORTE Data Latch
xxxx xxxx 60, 131
PORTD
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx 60, 128
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx 60, 125
PORTB
PORTA
Read PORTB pins, Write PORTB Data Latch
RA7(5)
RA6(5) Read PORTA pins, Write PORTA Data Latch
xxxx xxxx 60, 122
xx0x 0000 60, 119
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 75
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