PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
the initialization process. The Hash Pointer Array contains a total of 8192
pointers.
The first 1024 bytes of the operating environment are normally cached by the Switch
Processor in the data cache. As the data cache uses a write-back policy, the actual
memory locations corresponding to the cached structures may be out-of-date (i.e., not
reflect the most recent information written to the locations by the firmware). For
instance, the per-port SNMP counters contained within the Local Port Descriptors are
cached, and hence the memory images of the per-port counters may not be up-to-date.
Thus the Switch Processor must be forced to flush the data cache to update the
external memory locations prior to reading them from an external CPU via the PCI bus.
This can be accomplished via the messaging interface described further within this
section.
It is the responsibility of the bootstrap and initialization firmware contained within the
boot image to set up and initialize the entire operating environment described above.
Variables and Tables in Operating Environment
In addition to the major data structures (i.e., the register save space, the local and
expansion port descriptors, the port descriptor error counters, and the hash pointer
array), the Switch Processor operating environment contains a number of variables and
tables used during normal operation. Some of these memory locations (those located
between addresses 0x002000 and 0x0023ff in the memory map above) are normally
expected to be cached in the Switch Processor data cache, while the remainder are
never loaded into the data cache by the operating firmware. This section describes
these variables and their expected values.
The remainder of This section is TBD.
Packet Buffers
Ethernet packets are stored in the external RAM by the ELAN 8x10 chip in small, fixed
length packet buffers; multiple packet buffers are chained in a linked list to hold a
complete Ethernet packet. The size of the packet buffers is determined at configuration
time, and may range from 64 to 240 bytes; the default is 80 bytes.
Each packet buffer contains an 8-byte header holding various control information, and
from 0 to at most (N - 8) bytes of payload, comprising Ethernet frame data. (In this
context 'N' denotes the total size of each packet buffer: the default 80-byte packet
buffers will contain at most 72 bytes of payload.) The Ethernet data stored in the packet
buffers includes the Ethernet header and CRC fields.
A MAC channel byte-swap control bit is implemented on a channel-by-channel basis in
the LWCTRL device control register (see register descriptions below). If the byte swap
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