PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
• One channel is used to perform block transfers from the local memory to
external memory space accessible via the PCI expansion bus. This channel is
not intended to handle packet data; it is generally used for special control and
inter-device communication functions.
• The last channel facilitates the packet exchange handshake that takes place
between multiple ELAN 8x10 devices located on the same PCI bus. This
channel can be set up to perform up to seven writes in a single series of PCI
transactions to special request and acknowledge counters in up to seven
external ELAN 8x10 devices. The request and acknowledge counters are used
to indicate the presence of a packet being forwarded and to acknowledge
receipt of the packet, respectively.
Transfers are initiated under firmware control by the Switch Processor. In operation,
the Switch Processor loads the appropriate locations within the DMA register file with
the desired transfer parameters, and then enables the channel using the DMA control
register. The DMA Controller logic then reads out the transfer parameters into internal
temporary registers, performs the transfer, and updates the register file. The DMA
automatically multiplexes channel transfers by switching to a new channel after a burst
of up to 4 data words (i.e., 16 bytes) has been read or written, thus minimizing latency.
Memory Controller
An external memory is required to hold packet buffers for received and transmitted
Ethernet packets, as well as data structures needed to perform switching and support
system management. The external memory may also contain extension firmware for
the on-chip Switch Processor. The ELAN 8x10 therefore contains an integral memory
controller unit to support a variety of standard memories without glue logic.
The memory controller addresses a total of 16,777,216 bytes (16 megabytes) of EDO
DRAM, ROM, EPROM and EEPROM (either separately or in combination). The
address space is divided into four banks, each of which has an independently
programmable access time. This allows a mix of fast and slow devices to be used in
the system. Memory device types or speeds cannot be mixed within a bank (i.e., a
bank cannot consist of part EDO DRAM and part EPROM, for example). Memory
devices of different types must be assigned to different banks, and selected with
different chip selects.
Programming of EEPROM devices is done under control of Switch Processor
microcode.
To support memories other than those listed above, or special applications, a memory
ready input pin (MRDY_) is provided. This pin is sampled by the ELAN 8x10 when
accessing memories in asynchronous SRAM mode; it may be driven inactive prior to
the end of any memory cycle by an external memory timing generator to suitably
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
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