PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
lengthen the access cycle. The MRDY_ pin should be tied LOW (permanently asserted)
if it is not used.
The ELAN 8x10 generates four separate write enables to enable individual bytes within
each addressed 32-bit word to be written to independently of the others. This allows
the ELAN 8x10 to perform byte (8-bit), halfword (16-bit), tribyte (24-bit) and fullword (32-
bit) memory accesses without using read-modify-write operations.
An interrupt pin (MINTR_) is provided for special applications. A LOW level on this pin
causes an interrupt to be generated to the internal Switch Processor, the PCI bus (via
the INT_ output), or both. The use of this interrupt input is application dependent and
beyond the scope of this datasheet. The MINTR_ pin should be tied HIGH (de-
asserted) if it is not used.
The memory controller is capable of sustaining a throughput of 84 Mbytes/s (672
Mbit/s) to and from standard EDO DRAM devices, with peak throughputs of 100
Mbytes/s during burst accesses.
PCI Expansion Port
The ELAN 8x10 includes a PCI v2.1 compatible bus master and slave interface, which
serves as an expansion port allowing multiple ELAN 8x10s to be seamlessly
interconnected in the same system. The expansion port supports a maximum PCI bus
clock of 40 MHz (resulting in a >1 Gbit/s peak transfer rate and a sustained throughput
of over 400 Mbit/s), and contains several FIFOs to increase burst throughput and
perform clock synchronization. This port may be used for expanding a switch built
around 8-port ELAN 8x10 chips (to a maximum of 64 ports In this application, the on-
chip DMA Controller uses the PCI master interface to notify other ELAN 8x10 devices
of the presence of packets to be transferred, and to copy packets or data structures
under control of the Switch Processor between external ELAN 8x10 devices to the local
memory space. Note that data are never transferred directly between the MAC
channels and the PCI bus.
The PCI bus master interface serves to allow the DMA controller as well as the CPU to
initiate transactions on the PCI bus. The bus master is compatible with the PCI v2.1
specifications for standard transaction initiator devices, and can perform configuration
space as well as memory space read and write transfers. (Note that the ELAN 8x10
does not support I/O space transactions.) The PCI bus master unit contains a 64-byte
write FIFO to buffer data being written by the ELAN 8x10 device to an external target on
the PCI bus, as well as a 128-byte read FIFO to hold data that has been read from an
external target. These FIFOs permit the bus master to operate using long burst
transactions for increasing the PCI bus bandwidth utilization. The bus master interface
is also compatible with the PCI v2.1 latency timer requirements, and supports back-to-
back transfers.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
50
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