PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
MDATA[29]
MDATA[28]
MDATA[27]
MDATA[26]
MDATA[25:22]
MDATA[21:16]
MDATA[15:14]
MDATA[13]
MDATA[12]
MDATA[11:9]
MDATA[8:6]
PM3350 ELAN 8 X10
ISSUE 3
8 PORT ETHERNET SWITCH
RSTTM
IMDIS
PCI3V
FIRM
CHIPID[3:0]
RTCDIV[5:0]
MXSEL[1:0]
MSLO
MDCAS
MTYPE3[2:0]
MTYPE2[2:0]
For test purposes only. Pull low for correct operation.
Internal memory disable: if high, the internal Switch Processor
ROM is disabled at initialization time.
If high, configures the PCI interface for the 3.3V signaling
environment. If low, configures the PCI interface for the 5V
signaling environment. Must be set to logic 0 since all AC
parametric testing done with the 5V signaling conditions.
Reserved for use by Switch Processor firmware.
These bits determine the PCI memory base address at
initialization time if the PCIRUN configuration bit is high. In this
case, the CHIPID[3:0] inputs are zero-extended to 8 bits and
loaded into the most significant byte of the Memory Base
Address register in the PCI configuration register space.
Real time clock divider: selects the divide ratio used for the
internal real-time clock prescaler. This field must be set
numerically equal to the frequency, in megahertz, of the clock
supplied on the SYSCLK input.
These inputs select the row/column multiplexing used for EDO
DRAM devices.
MXSEL
00
01
10
11
Column
Address Bits
8
9
10
11
DRAM Configurations
Supported
64K x N & 128K x N
256K x N & 512K x N
1024K x N & 2048K x N
4 Meg x N & 8 Meg x N
The MSLO bit extends read and write cycles to accommodate
slower local memory devices. If MSLO is high, memory
accesses will be to 80ns DRAM. If MSLO is low, 60ns DRAM is
expected. The PM3350 is intended to be used with 60ns EDO
DRAM; hence, MSLO must be a logic 0. The access time for
ROM is always 150ns, respectively, regardless of the state of the
MSLO bit.
This bit identifies the type of DRAM connected to the
memory interface. If MDCAS is high, the memory interface
will generate control signals for 2-CAS DRAMs; otherwise,
it generates signals for single CAS DRAMs.
Indicates the type of memory connected to the MCS[3]* output:
MTYPE3[2:0]
000
001
010
011
100
101
110
111
Selected memory type
Reserved
Reserved
Reserved
Reserved
Reserved
200ns (E)EPROM
60ns EDO DRAM
Reserved
Indicates the memory type associated with MCS[2]*. The
encoding is the same as for MTYPE3[2:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
57
Share Link: 
