PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
Configuration and Initialization
Initialization and configuration can be considered as either a two step or four step
process. The two-step process is the default, and used for most normal applications;
the four-step process may be followed to over-ride the default configuration information
for special purposes.
Two-step process
For a two-step process all of the basic device and system configuration information is
taken from the local memory interface of this ELAN 8x10 chip using this sequence:
• Basic hardware configuration information, comprising a 32-bit device and
memory configuration word, is latched by the ELAN 8x10 from the memory data
lines into internal registers upon RST_ transitioning high (i.e., upon the trailing
edge of a hardware reset). The 32-bit configuration word is held in the
MCONFIG (Memory Configuration) and DCONFIG (Device Configuration)
registers.
• The remaining device configuration and initialization information is obtained
automatically by the ELAN 8x10 by scanning for an external EPROM or
EEPROM, and reading a bootstrap image from it. The bootstrap image contains
a number of system-dependent configuration parameters, the operating
firmware for the Switch Processor, and any code required for a Real-Time
Operating System, SNMP agent, spanning tree processing, etc.
Four-step process
For a four-step process not all of the basic device and system configuration is taken
from the local memory of this ELAN 8x10 chip: an external host processor, or a master
ELAN 8x10 device, is expected to modify or download configuration and bootstrap data.
1. Configuration information is latched from the memory data lines into internal
registers upon RST_ transitioning high as described above. The RISCRUN bit
(bit 30, see the next section) of the 32-bit configuration data word must be
cleared to ensure that the Switch Processor enters a halt state immediately after
reset. The PCIRUN bit (bit 31) of the configuration data word may also be
cleared if the external host processor intends to carry out the normal PCI
configuration register setup process as per the PCI specification.
2. The DCONFIG and MCONFIG registers of the device are accessible via the PCI
bus interface, and may be modified if necessary by the system master. It is also
possible for the system master to download a preformatted bootstrap image to
the RAM interfaced to the device; the ELAN 8x10 will locate the bootstrap image
and self-initialize from it.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
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