PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
Watchdog Timer Facility
The ELAN 8x10 device incorporates a simple internal watchdog timer that optionally
initiates an automatic system hardware reset if some catastrophic error occurs that
causes the Switch Processor to lock up or enter an undefined state. The watchdog
timer is built around the 16-bit WTIMER device control register (described in more detail
in a later section).
The WTIMER register principally acts as a down-counter, decrementing its value by 1
every millisecond until it reaches zero. Firmware running on the Switch Processor will,
under normal circumstances, periodically reload the WTIMER register with a non-zero
value before it reaches zero. If however, the Switch Processor firmware encounters
some serious system fault that prevents it from reloading the WTIMER register before it
has counted down to zero, the watchdog facility will assert the ERST_ output LOW for
one millisecond. If the ERST_ output is tied to the system reset line (this is made
possible by the fact that ERST_ is an open-drain output), then the watchdog timer
facility will effectively reset the entire system. Alternatively, the ERST_ output can tied
to a resistive pull-up and simply monitored by an external system processor; a hardware
or software reset of the ELAN 8x10 device should be performed if the ERST_ output
goes LOW.
The value used by the Switch Processor firmware to reload the WTIMER register is a
configurable parameter, and should be chosen to ensure that false system resets do
not occur under high loads without simultaneously incurring an excessive system
recovery time. The maximum reload interval is approximately 65 seconds; the minimum
interval is about 2 milliseconds. A value of 1-2 seconds is recommended.
If the WTIMER register is loaded with all-ones (0xffff hex) the watchdog timer facility will
be disabled, and the WTIMER register will be prevented from counting down and
asserting the ERST_ output. (The watchdog facility can hence be disabled by the
system implementer by setting the configurable reload value to 0xffff hex.) Note that the
WTIMER register rolls over to 0xffff after it has counted down to zero, thereby
automatically disabling itself after the 1 millisecond reset duration is over. If the
WTIMER register is left untouched by the initialization process, then it will default to a
disabled state, i.e., it will remain loaded with 0xffff and, as a result, will not count down.
If the Switch Processor itself detects an unrecoverable fault that requires a general
system reset, then the Switch Processor firmware will write a value of zero to the
WTIMER register under program control. This will cause the ERST_ pin to be
immediately asserted (driven LOW), potentially causing a hardware reset or notifying
the system processor that a fault has occurred.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
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