PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
3. A software reset is performed to the device using the HCTRL register, also
accessible via the PCI bus, by writing the GRES bit first to a logic 1 and then to
a logic 0. Note that GRES must remain asserted a minimum of 128 PCI clock
cycles. The updated DCONFIG and MCONFIG register information will be
internally latched upon de-assertion of the GRES bit.
4. The remaining device configuration and initialization will be obtained by
scanning for and reading a bootstrap image contained in an external EPROM or
EEPROM, or downloaded into system RAM by the master processor.
Device Configuration
Basic device and system configuration (i.e., memory types and speeds for various
banks, the PCI base address for this ELAN 8x10 device, and auto-boot and
master/slave enable flags) are supplied by means of resistor pull-ups and pull-downs
connected to the 32-bit data bus. This configuration information is latched into internal
registers upon the second SYSCLK rising edge after the RST_ input to the ELAN 8x10
transitions high, and sets up the ELAN 8x10 internal hardware. The 32 bits of
configuration data presented on the memory data bus are latched into the 16-bit
DCONFIG and MCONFIG registers internal to the ELAN 8x10; these registers may also
be accessed by the Switch Processor and by external devices via the PCI bus.
As an alternative to resistor pull-ups and pull-downs, a tri-state buffer or tri-statable
register may be used to drive configuration information on to the data bus during reset.
Care should be taken to remove the data by tri-stating the buffer or register no earlier
than 2 SYSCLK periods after the trailing edge of the RST* input, and no later than 10
SYSCLK periods after the latter (to prevent memory data bus contention).
The memory data bus is mapped to configuration bits as follows:
Device Pin
MDATA[31]
MDATA[30]
Register Bit
PCIRUN
RISCRUN
Description
This input selects the default operating mode of the PCI
interface.
If logic 1:
• The on-chip PCI interface latches its slave memory base
address from the CHIPID configuration bits (MDATA[25:22]).
• The PCI Command Register bits for "Bus Master" and
"Memory Space" are set (1), thereby allowing the device to
respond to PCI memory space accesses and to be a bus master.
If logic 0
• The PCI interface has a memory base address of 0.
• The PCI Command Register bits for "Bus Master" and
"Memory Space" are cleared (0); the device is disabled from
responding to PCI memory space accesses and will not be a bus
master.
A low on this signal halts the Switch Processor upon reset,
effectively placing the device into stand-by mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
56
Share Link: 
