PM3350-SW View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350-SW' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
• memory read
• memory write
• configuration read
• configuration write
The on-chip PCI interface supports the following PCI commands as a target:
• memory read
• memory write
• configuration read
• configuration write
• memory read multiple
• memory read line
• memory write and invalidate
PCI Vendor ID and Device Number
The vendor ID assigned to the ELAN 8x10 device (in the PCI configuration register
space) is 11F8 hexadecimal, while the device number is 3350 hexadecimal. The class
code for the ELAN 8x10 is set to 0x020000 hexadecimal.
Slave Read Prefetching
The PCI bus slave logic contains a 128-byte read FIFO buffer to speed up reads made
from this ELAN 8x10 device over the PCI bus. This FIFO has a prefetch capability that
is activated when accessing external memory space: it attempts to read ahead and
speculatively obtain more data words than have been actually requested by the
transaction master, thereby potentially increasing the efficiency of burst transfers.
The prefetch capability functions as follows. Initially, the PCI slave read FIFO is empty,
and remains so until the PCI slave is idle. When a read transaction is initiated by an
external bus master, the PCI slave logic will perform a disconnect with retry (after a
configurable amount of cycles) because the read FIFO is empty and no data can be
returned. The slave logic then decodes the target address of the read: if it corresponds
to external memory space, then the prefetch capability is activated. The slave logic
subsequently requests the memory controller to begin fetching from the target memory
address; the data returned are placed into the slave read FIFO, and the PCI slave logic
continues to fetch additional data words at consecutive addresses until the slave read
FIFO is full. Up to 128 bytes of data may be fetched in this way and placed into the
slave read FIFO.
At some point, the original PCI transaction initiator (bus master) is expected to retry the
access. (According to the rules of the PCI bus, it is an error for the bus master to
abandon an access that has been terminated with a disconnect-and-retry.) The PCI
slave logic will compare the address being requested by the PCI bus master for the
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