PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
Pin Name Pin Type Pin Function
No.
GRICLK Output
134 When either of the bit serial receive interfaces
are enabled, GRICLK is the generated byte
serial clock. When the bit serial STS-1 mode is
enabled, GRICLK is a 6.48 MHz clock that is
generated by dividing the receive serial
incoming clock (RSICLK) by eight. When the
bit serial STS-3 mode is enabled, GRICLK is a
19.44 MHz clock that is generated by dividing
the receive serial incoming clock (RSC+/-) by
eight. GRICLK must be externally shorted
directly to the receive incoming clock (RICLK)
when processing a bit serial stream.
ROUT[7]
ROUT[6]
ROUT[5]
ROUT[4]
ROUT[3]
ROUT[2]
ROUT[1]
ROUT[0]
ROFP
Output
Output
Output
Output
Output
Output
Output
Output
Output
TSER
Input
123 ROUT[7:0] contains the descrambled outgoing
124
stream in byte serial format. ROUT[7] is the
most significant bit (corresponding to bit 1 of
125 each serial PCM word, the first bit received).
126 ROUT[0] is the least significant bit
(corresponding to bit 8 of each serial PCM
127 word). ROUT[7:0] is updated on the rising
128 edge of RICLK.
131
132
133 The active high receive outgoing frame position
(ROFP) signal is set high once per frame in the
byte position immediately following the Z0
bytes in the ROUT[7:0] stream. ROFP is also
used to mark the alignment of the RSOW,
RSUC, RLOW and RAPS bit streams.
ROFP is updated on the rising edge of RICLK.
12 The transmit serial input (TSER) selects the
transmit line interface. TSER is tied high to
select the bit serial interface on PECL pins
TXCI+, TXCI-, TXCO+, TXCO-, TXD+, and
TXD-. A TTL interface is also supported in
STS-1 mode on pins TSICLK and TSOUT.
TSER is tied low to select the byte serial
interface on pins TICLK, TOFP, and TOUT[7:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18
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