PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
Pin Name Pin Type Pin Function
No.
TICLK/
Input
TVCLK
140 The transmit incoming clock (TICLK) provides
timing for processing the transmit stream,
TIN[7:0]. TICLK is nominally a 6.48 MHz (STS-
1), or 19.44 MHz (STS-3/STM-1) 50% duty
cycle clock, depending on the selected
operating mode. TIN[7:0], and TIFP are
sampled on the rising edge of TICLK. TICLK
must be externally shorted directly to GTICLK
when processing bit serial transmit streams.
The transmit vector clock (TVCLK) is used
during STXC production test to verify internal
functionality.
GTICLK Output
TSICLK Input
TXCI+
TXCI-
PECL
Input
141 When either of the bit serial transmit interfaces
are enabled, GTICLK is the generated byte
serial clock. GTICLK is a 6.48 MHz or 19.44
MHz clock that is generated by dividing the
transmit serial incoming clock (TSICLK or
TXCI+/-) by eight. GTICLK must be externally
shorted directly to the transmit incoming clock
(TICLK) when processing a bit serial stream.
In line loopback mode operation (LLE bit set
high), GTICLK is generated by dividing the
RXC+/- inputs by eight.
11 The transmit serial incoming clock (TSICLK)
provides timing for updating the bit serial
outgoing stream when STS-1 mode is selected.
TSICLK is nominally a 51.84 MHz, 50% duty
cycle clock. TSOUT is updated on the rising
edge of TSICLK. The TSICLK input has an
integral pull down resistor. The device may be
configured to use the TXCI+/- inputs as the
serial clock.
28 The transmit differential clock inputs (TXCI+,
27 TXCI-) provide timing for updating the bit serial
outgoing stream. TXCI+/- is nominally a 155.52
MHz or 51.84 MHz, 50% duty cycle clock. The
TSICLK is the default clock for the 51.84 Mbit/s
data rate.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19
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