PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
observed in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames.
Line AIS is removed when any pattern other than 111 is observed for three or
five consecutive frames. Line far end receive failure is declared (RDI is set high)
when the bit pattern 110 is observed in bits 6, 7, and 8 of the K2 byte for three or
five consecutive frames. Line RDI is removed when any pattern other than 110 is
observed for three or five consecutive frames.
The automatic protection switch bytes (K1, K2) are also extracted into the
Receive K1 Register and the Receive K2 Register. The bytes are filtered for
three frames before being written to these registers. A protection switching byte
failure alarm is declared when twelve successive frames have been received,
where no three consecutive frames contain identical K1 bytes. The protection
switching byte failure alarm is removed upon detection of three consecutive
frames containing identical K1 bytes. The detection of invalid APS codes is done
in software by polling the Receive K1/K2 Registers
The line level bit-interleaved parity (B2) is computed, and compared to the
received B2 bytes. Line BIP-8 errors are accumulated in an internal counter.
Registers are provided that allow accumulated line BIP-8 errors to be read out at
intervals of up to one second duration. A line BIP-8 error clock is also provided
(B2E).
Signal fail (SF) and signal degrade (SD) threshold crossing alarms are detected
and indicated using internal register bits. The bit error rates associated with the
SF and SD alarms are programmable over a range of 10-3 to 10-9. The Bit Error
Rate Monitor (BERM) circuit block extracts the Automatic Protection Switch
(APS) bytes (K1 and K2), extracts the Synchronization Status byte (Z1), and
processes the Line BIP-8 (B2) error signal. A protection switching byte failure
alarm is declared when twelve successive frames have been received, where no
three consecutive frames contain identical K1 bytes. The protection switching
byte failure alarm is removed upon detection of three consecutive frames
containing identical K1 bytes. The detection of invalid APS codes is done in
software by polling the APS K1 Register and the APS K2 Register.
The received line BIP-8/24 error detection code (B2) byte is based on the line
overhead and synchronous payload envelope of the receive stream. The line BIP
code is a bit interleaved parity calculation using even parity, and the calculated
BIP code is compared with the BIP code extracted from the B2 bytes of the
following frame. Any differences indicate that a line layer bit error has occurred.
Up to 192000 (24 BIP/frame x 8000 frames/seconde) bit errors can be detected
per second for STS-3 rate and 64000 (8 BIP/frame x 8000 frames/seconde) for
STS-1 rate.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 38
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