PM6670AS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PM6670AS' PDF : 54 Pages View PDF
Device description
PM6670AS
Figure 29. Circuitry for output ripple compensation
COMP PIN
VOLTAGE
Vr
ΔV
t
OUTPUT
VOLTAGE
ΔV
t
COMP
CFILT
CINT
RINT
VCINT
VREF
I=gm(V1-Vr)
+
-
PWM
Comparator
gm
+ RFb1
Vr
V1
RFb2
ESR
COUT
VSNS
The additional capacitor is used to reduce the voltage on the COMP pin when higher than
300 mVpp and is unnecessary for most of applications. The trans conductance amplifier
(gm) generates a current, proportional to the DC error, used to charge the CINT capacitor.
The voltage across the CINT capacitor feeds the negative input of the PWM comparator,
forcing the loop to compensate the total static error. An internal voltage clamp forces the
COMP pin voltage range to ±150 mV with respect to VREF. This is useful to avoid or smooth
output voltage overshoot during a load transient. When the pulse-skip mode is entered, the
clamping range is automatically reduced to 60mV in order to enhance the recovering
capability. In the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can
be connected between the COMP pin and ground to reduce ripple amplitude, otherwise the
integrator will operate out of its linearity range. This capacitor is unnecessary for most of
applications and can be omitted.
The design of the external feedback network depends on the output voltage ripple. If the
ripple is higher than approximately 20mV, the correct CINT capacitor is usually enough to
keep the loop stable. The stability of the system depends firstly on the output capacitor zero
frequency.
The following condition must be satisfied:
Equation 6
fSW
>
k ⋅ fZout
=
k
2π ⋅ Cout
⋅ ESR
where k is a fixed design parameter (k > 3). It determines the minimum integrator capacitor
value:
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Doc ID 14436 Rev 2
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