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PSD813F1AV-12J View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'PSD813F1AV-12J' PDF : 110 Pages View PDF
PSD813F1V
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the microcontroller by a factor of up to
256. The contents of the register can also be read
by the microcontroller. The outputs of the Page
Register (PGR0-PGR7) are inputs to the DPLD
decoder and can be included in the Flash Memory,
EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure 14. Page Register
RESET
Figure 14 shows the Page Register. The eight flip
flops in the register are connected to the internal
data bus D0-D7. The microcontroller can write to
or read from the Page Register. The Page Regis-
ter can be accessed at address location CSIOP +
E0h.
D0
Q0
D1
Q1
D0 - D7 D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
R/W
D7
Q7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
Flash DPLD
AND
Flash CPLD
PLD
INTERNAL
SELECTS
AND LOGIC
AI09224
33/110
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