PSD813F1AV-12J View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD813F1AV-12J
STMicroelectronics
'PSD813F1AV-12J' PDF : 110 Pages View PDF
PSD813F1V
DECODE PLD (DPLD)
The DPLD, shown in Figure 16, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■ 8 sector selects for the main Flash memory
(three product terms each)
■ 4 sector selects for the EEPROM (three
product terms each)
Figure 16. DPLD Logic Array
■ 1 internal SRAM select signal (two product
terms)
■ 1 internal CSIOP (PSD configuration register)
select signal
■ 1 JTAG select signal (enables JTAG on Port
C)
■ 2 internal peripheral select signals (peripheral
I/O mode).
I /O PORTS (PORT A,B,C)
(INPUTS)
(24)
MCELLAB.FB [7:0] (FEEDBACKS)
(8)
MCELLBC.FB [7:0] (FEEDBACKS)
(8)
PGR0 - PGR7
(8)
A[15:0](1)
(16)
PD[2:0] (ALE,CLKIN,CSI)
(3)
PDN (APD OUTPUT)
(1)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)
RESET
(1)
RD_BSY
(1)
3
EES 0
3
EES 1
EEPROM
3
EES 2
SELECTS
3
EES 3
3
FS0
3
FS1
3
FS2
3
FS3 8 FLASH MEMORY
3
SECTOR SELECTS
FS4
3
FS5
3
FS6
3
FS7
2
RS0
SRAM SELECT
1
CSIOP
I/O DECODER
SELECT
1
PSEL0
PERIPHERAL I/O
1
PSEL1
MODE SELECT
1
JTAGSEL
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
AI09226
36/110
Share Link: 