QL5030 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5030
QuickLogic Corporation
'QL5030' PDF : 18 Pages View PDF
QL5030 QuickPCI Data Sheet
Table 8: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
8
tSRA
RA Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
tHRA
RA Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
tSRE
RE Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
tHRE
RE Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
tRCRD RCLK to RD [5]
4.0
4.3
4.6
4.9
6.1
Table 9: RAM Cell Asynchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
8
rPDRD RA to RD [5]
3.0
3.3
3.6
3.9
5.1
Table 10: Input-Only Cells
Symbol
Parameter
Propagation Delays (ns)
Fanout [a]
1 2 3 4 8 12 24
tIN
High Drive Input Delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
tINI High Drive Input, Inverting Delay
1.6 1.7 1.9 2.0 2.5 3.0 4.5
tISU Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1 3.1
tIH
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
tlCLK Input Register Clock To Q
0.7 0.8 1.0 1.1 1.6 2.1 3.6
tlRST Input Register Reset Delay
0.6 0.7 0.9 1.0 1.5 2.0 3.5
tlESU Input Register Clock Enable Setup Time
2.3 2.3 2.3 2.3 2.3 2.3 2.3
tlEH Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
a. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
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