QL5030 View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5030

33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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QL5030 QuickPCI Data Sheet

Table 11: Clock Cells

Symbols

Parameter

Propagation Delays (ns)

Loads per Half Column [a]

1

2

3

4

8 10 12 15

tACK Array Clock Delay

1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8

tGCKP Global Clock Pin Delay

0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7

tGCKB Global Clock Buffer Delay

0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4

a. The array distributed networks consist of 40 half columns and the global distributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used

does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global

clock has up to 11 loads per half column.

Table 12: I/O Cell Input Delays

Symbol

Parameter

Propagation Delays (ns)

Fanout [5]

1 2 3 4 8 10

tI/O Input Delay (bidirectional pad)

1.3 1.6 1.8 2.1 3.1 3.6

tISU Input Register Set-Up Time

3.1 3.1 3.1 3.1 3.1 3.1

tIH Input Register Hold Time

0.0 0.0 0.0 0.0 0.0 0.0

tlOCLK Input Register Clock To Q

0.7 1.0 1.2 1.5 2.5 3.0

tlORST Input Register Reset Delay

0.6 0.9 1.1 1.4 2.4 2.9

tlESU Input Register clock Enable Set-Up Time

2.3 2.3 2.3 2.3 2.3 2.3

tlEH Input Register Clock Enable Hold Time

0.0 0.0 0.0 0.0 0.0 0.0

QL5030 QuickPCI Data Sheet Rev C

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