QL5030 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5030
QuickLogic Corporation
'QL5030' PDF : 18 Pages View PDF
QL5030 QuickPCI Data Sheet
12.0 QL5030 External Device Pins
The QL5030 Device Pins are indicated in Table 14 and Table 15 below. These are pins on the device,
some of which connect to the PCI bus, and others that are programmable as user I/O.
Table 14: Pin Type Descriptions
Type
Description
IN Input. A standard input-only signal
OUT Totem pole output. A standard active output driver
T/S Tri-state. A bi-directional, tri-state input/output pin
Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven
S/T/S
high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the
PCI system central resource to sustain the inactive state once the active driver has released the
signal.
O/D Open Drain. Allows multiple devices to share this pin as a wired-or.
Table 15: Device Pins
Pin/Bus Name Type
Function
VCC
IN Supply pin. Tie to 3.3V supply.
VCCIO
IN Supply pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O
GND
IN Ground pin. Tie to GND on the PCB.
I/O
T/S Programmable Input/Output/Tri-State/Bi-directional Pin.
GLCK/I
IN Programmable Global Network or Input-only pin. Tie to VCC or GND if unused.
ACLK/I
IN Programmable Array Network or Input-only pin. Tie to VCC or GND if unused.
TDI/RSI*
IN
JTAG Data In/Ram Init. Serial Data In. Tie to VCC if unused. Connect to Serial
EPROM data for RAM init.
TDO/RCO*
OUT
JTAG Data Out/Ram Init Clock. Leave unconnected if unused. Connect to Serial
EPROM clock for RAM init.
TCK
IN JTAG Clock. Tie to GND if unused.
TMS
IN JTAG Test Mode Select. Tie to VCC if unused.
TRSTB/RRO*
IN
JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM
reset for RAM init.
STM
IN QuickLogic Reserved pin. Tie to GND on the PCB.
NOTE: *See QuickNote 65 on the QuickLogic website for information on RAM initialization.
QL5030 QuickPCI Data Sheet Rev C
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