QL5032-33APB256C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5032-33APB256C
QuickLogic Corporation
'QL5032-33APB256C' PDF : 17 Pages View PDF
QL5032 - QuickPCITM
PCI Controller
PCI CONTROLLER
The PCI Controller is a 32-bit/33 MHz PCI 2.2
Compliant Master/Target Controller. It is capable of
infinite length Master Write and Read transactions at
zero wait state (132 MBytes/second). The Master
will never insert wait states during transfers, so data
should be supplied or received by FIFOs, which can
be configured in the programmable region of the
device. The Master Controller will most often be
operated by a DMA Controller in the programmable
region of the device. A DMA Controller reference
design is available. The Target interface offers full
PCI Configuration Space and flexible target address-
ing. Any number of 32-bit BARs may be configured,
as either memory or I/O space. All required and
options PCI 2.2 Configuration Space registers can be
implemented within the programmable region of the
device. A reference design of a Target Configuration
and Addressing module is provided.
The interface ports are divided into a set of ports for
master transactions and a set for target transactions.
The Master DMA controller and Target Configura-
tion Space and Address Decoding are done in the
programmable logic region of the device. Since
these functions are not timing critical, leaving these
elements in the programmable region allows the
greatest degree of flexibility to the designer. Refer-
ence DMA controller, Configuration Space, and
Address Decoding blocks are included so that the
design cycle can be minimized.
ConCfiOguNrFaItGioUnRSApTaIcOeNanSdPAAdCdEress
AND ADDDReEcoSdSe DECODE
The configuration space is completely customizable
in the programmable region of the device.
PCI address and command decoding is performed by
logic in the programmable section of the device. This
allows support for any size of memory or I/O space
for back-end logic. It also allows the user to imple-
ment any subset of the PCI commands supported by
the QL5032. QuickLogic provides a reference
Address Register/Counter and Command Decode
block.
DMADMMAAMSaTsEtRer//TTAarRgGeEt TCoCnOtrNoTlROL
The customizable DMA controller included with the
QuickWorks design software contains the following
features:
s Configurable DMA count size for reads and writes
(up to 30-bits)
s Configurable DMA burst size for PCI (including
unlimited/continuous burst)
s Programmable Arbitration between DMA Read &
Write transactions
s DMA Registers may be mapped to any area of
Target Memory Space
- Read Address (32-bit register)
- Write Address (32-bit register)
- Read Length (16-bit register) / Write Length
(16-bit register)
- Control and Status (32-bit register, includes 8 bit
Burst Length)
s DMA Registers are available to the local design or
the PCI bus
s Programmable Interrupt Control to signal end of
transfer or other event
Configurable FIFOs
CONFIGURABLE FIFOS
FIFOs may be created with the Ram/FIFO wizard in
the QuickWorks tools. The figure below shows the
graphical interface used to create these FIFOs.
FIFOs may be designed up to 256 deep. With 14
RAM cells available in the QL5032, that allows for
up to 7 FIFOs at 64 deep (36 wide), 3 FIFOs at 128
deep (36 wide), or 1 FIFO at 256 deep (36 wide).
FIGURE 2. Graphical Interface to create FIFO
2
2
Preliminary
Share Link: 