QL5032-33APB256C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5032-33APB256C
QuickLogic Corporation
'QL5032-33APB256C' PDF : 17 Pages View PDF
QL5032 - QuickPCITM
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The figure below shows the interface symbol you would use in your schematic design in order to attach the local
interface programmable logic design to the PCI core. If you were designing with a top-level Verilog or VHDL file,
then you would use a structural instantiation of this PCI32 block, instead of a graphical symbol.
CLK
RSTN
IDSEL
GNTN
PCI32
PCI Pads
AD[31:0]
CBEN[3:0]
FRAMEN
IRDYN
TRDYN
DEVSELN
STOPN
PAR
PERRN
SERRN
REQN
INTAN
PCI Signals
PCI_clock
PCI_reset
PCI_IRDYN_D1
PCI_FRAMEN_D1
PCI_DEVSELN_D1
PCI_TRDYN_D1
PCI_STOPN_D1
PCI_IDSEL_D1
Usr_RdData[31:0]
Usr_Select
Usr_Stop
Usr_Interrupt
Usr_Rdy
Usr_MstRdAd_Sel
Usr_MstWrAd_Sel
Usr_RdDecode
Usr_WrDecode
Cfg_RdData[31:0]
Cfg_LatCnt[7:0]
Cfg_CmdReg6
Cfg_CmdReg8
Target
Usr_WrReq
Usr_Write
Cfg_Write
Usr_Addr_WrData[31:0]
Usr_CBE[3:0]
Usr_Adr_Valid
Usr_Adr_Inc
Usr_Last_Cycle_D1
Usr_TRDYN
Usr_STOPN
Usr_Devsel
Cfg_PERR_Det
Cfg_SERR_Sig
Cfg_MstPERR_Det
Mst_WrMode
Mst_WrData[31:0]
Mst_WrData_Valid
Mst_WrAd[31:0]
Mst_RdMode
Mst_RdAd[31:0]
Mst_RdCmd[1:0]
Mst_One_Read
Mst_Two_Reads
Mst_Burst_Req
Mst_LatCntEn
Master
Mst_WrData_Rdy
Mst_WrBurst_Done
Mst_RdData[31:0]
Mst_RdData_Valid
Mst_RdBurst_Done
Mst_Xfer_D1
Mst_Last_Cycle
Mst_REQN
Mst_IRDYN
Mst_Tabort_Det
Mst_TTO_Det
FIGURE 3. PCI Interface Symbol
3
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