QL5032-33APB256C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5032-33APB256C

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QuickLogic Corporation 

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QL5032 - QuickPCITM

JTAG Support

JTAG Support

JTAG pins support IEEE standard 1149.1a to pro-

vide boundary scan capability for the QL5032

device. Six pins are dedicated to JTAG and program-

ming functions on each QL5032 device, and are

unavailable for general design input and output sig-

nals. TDI, TDO, TCK, TMS, and TRSTB are JTAG

pins. A sixth pin, STM, is used only for program-

ming.

DevDeelvoeplompmenentt TToooollSSuupppoprtort

Software support for the QL5032 device is available

through the QuickWorks® development package.

This turnkey PC-based QuickWorks® package,

shown in Figure 5, provides a complete ESP software

solution with design entry, logic synthesis, place and

route, and simulation. QuickWorks® includes

VHDL, Verilog, schematic, and mixed-mode entry

with fast and efficient logic synthesis provided by the

integrated Synplicity Synplify Lite™ tool, specially

tuned to take advantage of the QL5032 architecture.

QuickWorks also provides functional and timing sim-

ulation for guaranteed timing and source-level debug-

ging.

The UNIX-based QuickTools™ and PC-based Quick-

Works-Lite™ packages are a subset of QuickWorks®

and provide a solution for designers who use sche-

matic-only design flow third-party tools for design

entry, synthesis, or simulation. QuickTools™ and

QuickWorks-Lite™ read EDIF netlists and provide

support for all QuickLogic devices. QuickTools™

and QuickWorks-Lite™ also support a wide range of

third-party modeling and simulation tools. In addition,

the PC-based package combines all the features of

QuickWorks-Lite™ with the SCS schematic capture

environment, providing a low-cost design entry and

compilation solution.

Third Party

Design

Entry

& Synthesis

QuickWorksDesign Software

SCS

Tools

VHDL/

Schematic Verilog

Mixed-Mode Design

Turbo

HDL Editor

Third Party

Simulation

QuickTool/QuicChi:

Optimize, Place,

Route

Synplify-

HDL

Synthesi

Simulator

Silos III VeriBest

FIGURE 5. QuickWorks® Tool Suite

8

8

Preliminary

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