QL5130-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APQ208C
QuickLogic Corporation
'QL5130-33APQ208C' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
PCI Interface
PCI INTERFACE
The PCI target is PCI 2.2 compliant and supports
32-bit/33 MHz operation. It is capable of zero wait-
state infinite-length read and write transactions (132
MBytes/second). Transaction control is available via
the user interface as retries, wait-states, or premature
transaction termination may be induced if necessary.
The PCI configuration registers are implemented in
the programmable region of the device, leaving the
designer with ample flexibility to support optional
features.
The QL5130 device supports maximum 32-bit PCI
transfer rates, so many applications exist which are
ideally suited to the device’s high performance.
High-speed data communications, telecommunica-
tions, and computing systems are just a few of the
broad range of applications areas that can benefit
from the high speed PCI interface and programmable
logic.
PCPICCI COoNnFfIigGuUrRatAioTnIOSNpaScePACE
The QL5130 supports customization of required
Configuration Registers such as Vendor ID, Device
ID, Subsystem Vendor ID, etc.. QuickLogic provides
a reference Configuration Space design block.
Since the PCI Configuration Registers are imple-
mented in the programmable region of the QL5130,
the designer can implement optional features such as
multiple 32-bit Base Address Registers (BARs) and
multiple functions, as well as support the following
PCI commands: I/O Read, I/O Write, Memory Read,
Memory Write, Config Read (required), Configuration
Write (required), Memory Read Multiple, Memory
Read Line, and Memory Write and Invalidate. Addi-
tionally, the device supports Extended Capabilities
Registers, Expansion ROMs, power management,
CompactPCI hot-plug/hot-swap, Vital Product Data,
I20, and mailbox registers.
ADDRESS AND
COMMAND DECODE
PCI address and command decoding is performed by
logic in the programmable section of the device. This
allows support for any size of memory or I/O space
for back-end logic. It also allows the user to imple-
ment any subset of the PCI commands supported by
the QL5130. QuickLogic provides a reference
Address Register/Counter and Command Decode
block.
ARCAHrcIhTiEteCcTtuUrReEOOveVrvEieRwVIEW
The RAM modules in the programmable region can
be used to create configurable 32-bit FIFOs. Each
32-bit FIFO can be independently assigned to Target
address space for read pre-fetch or write posting.
Using the 12 QuickLogic RAM modules, the combi-
nations include:
• 6 independent 64-deep FIFO (2 RAMs each),
or
• 3 independent 128-deep FIFOs (4 RAMs each),
or
• a combination of the above that requires 12 or less
QuickLogic RAM Modules
Asynchronous FIFOs (with independent read and
write clocks) are also supported.
FIGURE 2. Graphical Interface to create FIFO
2
Rev B
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