QL5130-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APQ208C
QuickLogic Corporation
'QL5130-33APQ208C' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
The RAM modules are “dual-ported”, with
completely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports
support asynchronous and synchronous operation,
while the WRITE ports support synchronous opera-
tion. Each port has 18 data lines and 9 address lines,
allowing word lengths of up to 18 bits and address
spaces of up to 512 words. Depending on the mode
selected, however, some higher order data or address
lines may not be used.
The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ opera-
tion (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYNCRD
input high).
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules. This
approach allows up to 512-deep configurations as
large as 28 bits wide in the QL5130 device.
A similar technique can be used to create depths
greater than 512 words. In this case, address signals
higher than the eighth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer SELECT
signals.
JTAG SUPPORT
JTAG pins support IEJETEAGstSaunpdpaorrdt 1149.1a to provide
boundary scan capability for the QL5130 device. Six
pins are dedicated to JTAG and programming func-
tions on each QL5130 device, and are unavailable for
general design input and output signals. TDI, TDO,
TCK, TMS, and TRSTB are JTAG pins. A sixth pin,
STM, is used only for programming.
DEVELOPMENT TOOLS
Development Tools
Software support for the QL5130 device is available
through the QuickWorks“ development package. This
turnkey PC-based QuickWorks package, shown in Fig-
ure 6, provides a complete ESP software solution with
design entry, logic synthesis, place and route, and sim-
ulation. QuickWorks includes VHDL, Verilog, sche-
matic, and mixed-mode entry with fast and efficient
logic synthesis provided by the integrated Synplicity
Synplify Lite‘ tool, specially tuned to take advantage of
the QL5130 architecture. QuickWorks also provides
functional and timing simulation for guaranteed timing
and source-level debugging.
The UNIX-based QuickTools‘ and PC-based Quick-
Works-Lite‘ packages are a subset of QuickWorks and
provide a solution for designers who use schematic-
only design flow third-party tools for design entry, syn-
thesis, or simulation. QuickTools and QuickWorks-
Lite read EDIF netlists and provide support for all
QuickLogic devices. QuickTools and QuickWorks-Lite
also support a wide range of third-party modeling and
simulation tools. In addition, the PC-based package
combines all the features of QuickWorks-Lite with the
SCS schematic capture environment, providing a low-
cost design entry and compilation solution.
Third Party
Design
Entry
& Synthesis
QuickWorksDesign Software
SCS
Tools
VHDL/
Schematic Verilog
Mixed-Mode Design
Turbo
HDL Editor
Third Party
Simulation
SpDE
Synplify-
HDL
Synthesi
Simulator
Silos III VeriBest
FIGURE 6. QuickWorks Tool Suite
Rev B
7
Share Link: 