QL5130-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5130-33APQ208C
QuickLogic Corporation
'QL5130-33APQ208C' PDF : 17 Pages View PDF
QL5130 - QuickPCITM
QL5130 EXTERNAL DEVICE PINS
QL5130 External Device Pins
The QL5130 Device Pins are indicated in the table below. These are pins on the device, some of which connect
to the PCI bus, and others that are programmable as user IO.
Type
IN
OUT
T/S
S/T/S
O/D
Description
Input. A standard input-only
signal
Totem pole output. A standard
active output driver
Tri-state. A bi-directional, tri-
state input/output pin
Sustained Tri-state. An active
low tri-state signal driven by
one PCI agent at a time. It
must be driven high for at least
one clock before being dis-
abled (set to Hi-Z). A pull-up
needs to be provided by the
PCI system central resource to
sustain the inactive state once
the active driver has released
the signal.
Open Drain. Allows multiple
devices to share this pin as a
wired-or.
Pin/Bus Type
Name
VCC
IN
VCCIO IN
GND IN
I/O
T/S
GLCK/I IN
ACLK/I IN
TDI/
IN
RSI*
TDO/
RCO*
OUT
TCK
IN
TMS
IN
TRSTB/ IN
RRO*
STM
IN
Function
Supply pin. Tie to 3.3V supply.
Supply pin for I/O. Set to 3.3V for
3.3V I/O, 5V for 5.0V compliant I/O
Ground pin. Tie to GND on the PCB.
Programmable Input/Output/Tri-
State/Bi-directional Pin.
Programmable Global Network or
Input-only pin. Tie to VCC or GND if
unused.
Programmable Array Network or Input-
only pin. Tie to VCC or GND if
unused.
JTAG Data In/Ram Init. Serial Data In.
Tie to VCC if unused. Connect to
Serial EPROM data for RAM init.
JTAG Data Out/Ram Init Clock.
Leave unconnected if unused. Connect
to Serial EPROM clock for RAM init.
JTAG Clock. Tie to GND if unused.
JTAG Test Mode Select. Tie to VCC if
unused.
JTAG Reset/RAM Init. Reset Out. Tie
to GND if unused. Connect to Serial
EPROM reset for RAM init.
QuickLogic Reserved pin. Tie to GND
on the PCB.
* See QuickNote 65 on the QuickLogic web site for
information on RAM initialization.
8
Rev B
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