QL5632-33B-PQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632-33B-PQ208C
QuickLogic Corporation
'QL5632-33B-PQ208C' PDF : 39 Pages View PDF
QL5632 Enhanced QuickPCI Device Data Sheet Rev. C
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently
or effectively—these functions require high logic cell usage while garnering only moderate
performance results.
The QL5632 architecture allows for functionality above and beyond that achievable using
programmable logic devices. By embedding a dynamically reconfigurable computational unit, the
QL5632 device can address various arithmetic functions efficiently. This approach offers greater
performance than traditional programmable logic implementations. The embedded block is
implemented at the transistor level as shown in Figure 5.
RESET
S1
S2
S3
D
C
3-4
decoder
B
A
CIN
SIGN1
SIGN2
A[0:7]
8-bit
2-1
A[8:15]
Multiplier
mux
16-bit
Adder
DQ
17 inc. 17-bit
COUT Register
00
Q[0
01
3-1
mux
10
A[0:15]
CLK
B[0:15]
2-1
mux
Figure 5: ECU Block Diagram
The 10 QL5632 ECU blocks are placed next to the SRAM circuitry for efficient
memory/instruction fetch and addressing for DSP algorithmic implementations.
Ten 8-bit MAC functions can be implemented per cycle for a total of ~1 billion MACs/s when
clocked at 98 MHz. Additional multiply-accumulate functions can be implemented in the
programmable logic.
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