QL5632-33B-PQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632-33B-PQ208C
QuickLogic Corporation
'QL5632-33B-PQ208C' PDF : 39 Pages View PDF
QL5632 Enhanced QuickPCI Device Data Sheet Rev. C
FIN
FOUT
Frequency Divide
_..1
_.. 2
+
_.. 4
-
PLL Bypass
Filter
vco
Frequency Multiply
_..1
_..2
_..4
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Tree
Figure 6: PLL Block Diagram
Fin represents a very stable high-frequency input clock and produces an accurate signal reference.
This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass
through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal
and the local VCO form a control loop. The VCO is multiplied or divided down to the reference
frequency, so that a phase detector (the crossed circle in Figure 6) can compare the two signals.
If the phases of the external and local signals are not within the tolerance required, the phase
detector sends a signal through the charge pump and loop filter (Figure 6). The charge pump
generates an error voltage to bring the VCO back into alignment, and the loop filter removes any
high frequency noise before the error voltage enters the VCO. This new VCO signal enters the
clock tree to drive the chip's circuitry.
Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT
is explained in Table 15). This clock signal is meaningful only when the PLL is configured for
external use; otherwise, it remains in high Z state, as shown in the post-simulation waveform.
Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL
presented in Figure 6 controls the clock tree in the fourth Quadrant of its ESP. QuickLogic PLLs
compensate for the additional delay created by the clock tree itself, as previously noted, by
subtracting the clock tree delay through the feedback path.
For more specific information on the Phase Locked Loops, please refer to QuickLogic
Application Note 58.
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© 2003 QuickLogic Corporation
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