QL5632-33B-PQ208C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632-33B-PQ208C

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

Prev 11 12 13 14 15 16 17 18 19 20 Next

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

The modes for the ECU block are dynamically re-programmable through the programmable logic.

Instruction

S1 S2 S3

00 0

00 1

01 0

01 1

10 0

10 1

11 0

11 1

Table 13: ECU Mode Select Criteria

Operation

ECU Performancea, -B WCC

tPD

tSU

tCO

Multiply

7.0 ns max

Multiply-Add

9.4 ns max

Accumulateb

4.1 ns min

1.2 ns max

Add

3.3 max

Multiply (registered)c

10.2 ns min

1.2 ns max

Multiply- Add (registered)

10.2 ns min

1.2 ns max

Multiply - Accumulate

10.2 ns min

1.2 ns max

Add (registered)

4.1 ns min

1.2 ns max

a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.

b. Internal feedback path in ECU restricts max clk frequency to 224 MHz.

c. B [15:0] set to zero.

NOTE: Timing numbers in Table 13 represent -B Worst Case Commercial conditions.

PLLs

Instead of requiring extra components, designers simply need to instantiate one of the pre-

configured models (described in this section). The QuickLogic built-in PLLs support a wider range

of frequencies than many other PLLs. These PLLs also have the ability to be cascaded to support

different ranges of frequency multiplications or divisions, driving the device at a faster or slower

rate than the incoming clock frequency. Most importantly, they achieve a very short clock-to-out

time—generally less than 3 ns. This low clock-to-out time is achieved by the Phase Locked Loop

subtracting the clock tree delay through the feedback path, effectively making the clock tree delay

zero.

Figure 6 illustrates a typical QuickLogic ESP PLL.

© 2003 QuickLogic Corporation

•

www.quicklogic.com

•

•

13

•

•

•

Share Link: