QL5732-33BPS484C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5732-33BPS484C
QuickLogic Corporation
'QL5732-33BPS484C' PDF : 41 Pages View PDF
QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
Table 13: RAM Cell Synchronous & Asynchronous Read Timing
Symbol
Parameter: RAM Cell Synchronous Read Timing
tSRA
tHRA
tSRE
tHRE
tRCRD
rPDRD
RA setup time to RCLK: time the Read ADDRESS must be stable before the active
edge of the Read CLOCK
RA hold time to RCLK: time the Read ADDRESS must be stable after the active
edge of the Read CLOCK
RE setup time to WCLK: time the Read ENABLE must be stable before the active
edge of the Read CLOCK
RE hold time to WCLK: time the Read ENABLE must be stable after the active edge
of the Read CLOCK
RCLK to RD: time between the active Read CLOCK edge and the time when the
data is available at RD
RAM Cell Asynchronous Read Timing
RA to RD: time between when the Read ADDRESS is input and when the DATA
is output
Value
Min
Max
0.686 ns
-
0 ns
-
0.243 ns
-
0
-
-
4.38 ns
-
2.06 ns
Symbol
tISU
tIHL
tICO
tIRST
tIESU
tIEH
Table 14: Input Register Cell
Parameter: Input Cell Register Only
Value
Min Max
Input register setup time: time the synchronous input of the flip flop must be stable
before the active clock edge
3.12 ns
-
Input register hold time: time the synchronous input of the flip flop must be stable
after the active clock edge
0 ns
-
Input register clock to out: time taken by the flip flop to output after the active clock
edge
- 1.08 ns
Input register reset delay: time between when the flip flop is “reset”(low) and when
the output is consequently “reset” (low)
- 0.99 ns
Input register clock enable setup time: time “enable” must be stable before the
active clock edge
0.37 ns -
Input register clock enable hold time: time “enable” must be stable after the active
clock edge
0 ns
-
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