QL7120-5PT208M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7120-5PT208M' PDF : 41 Pages View PDF
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Traditional Programmable Logic architectures do not implement arithmetic functions
efficiently or effectively—these functions require high logic cell usage while garnering only
moderate performance results.
The QL7120 architecture allows for functionality above and beyond that achievable using
programmable logic devices. By embedding a dynamically reconfigurable computational unit,
the QL7120 device can address various arithmetic functions efficiently. This approach offers
greater performance than traditional programmable logic implementations. The embedded
block is implemented at the transistor level as shown in )LJXUH .
RESET
S1
S2
S3
CIN
SIGN1
SIGN2
A[0:7]
A[8:15]
D
C
3-4
decoder
B
A
8-bit
2-1
Multiplier
mux
16-bit
Adder
DQ
17 inc. 17-bit
COUT Register
00
01
3-1
mux
10
Q[0:16]
A[0:15]
CLK
B[0:15]
2-1
mux
)LJXUH (&8 %ORFN 'LDJUDP
The 12 QL7120 ECU blocks are placed next to the SRAM circuitry for efficient
memory/instruction fetch and addressing for DSP algorithmic implementations.
Twelve 8-bit Multiply-Accumulate (MAC) functions can be implemented per cycle for a total
of 1.2 billion MACs when clocked at 100 MHz. Additional MAC functions can be
implemented in the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable
logic as shown in 7DEOH .
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