QL7120-5PT208M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7120-5PT208M' PDF : 41 Pages View PDF
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Fout represents the clock signal that emerges from the output pad (the output signal
PLLPAD_OUT is explained in 7DEOH ). This clock signal is meaningful only when the PLL
is configured for external use; otherwise, it remains in high Z state, as shown in the post-
simulation waveform.
Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL
presented in )LJXUH controls the clock tree in the fourth Quadrant of its ESP. As previously
noted, QuickLogic PLLs compensate for the additional delay created by the clock tree itself
by subtracting the clock tree delay through the feedback path.
For more specific information on the Phase Locked Loops, please refer to Application Note
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QuickLogic PLLs have eight modes of operation, based on the input frequency and desired
output frequency—7DEOH indicates the features of each mode.
7DEOH 3// 0RGH )UHTXHQFLHV
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PLL_HFb
PLL_LF
PLL_MULT2HF
PLL_MULT2LF
PLL_DIV2HF
PLL_DIV2LF
PLL_MULT4
PLL_DIV4
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Same as input frequency
Same as input frequency
2 × input frequency
2 × input frequency
1/2 × input frequency
1/2 × input frequency
4 × input frequency
1/4 × input frequency
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66 MHz–150 MHz
25 MHz–133 MHz
50 MHz–125 MHz
16 MHz–50 MHz
100 MHz–250 MHz
50 MHz–100 MHz
16 MHz–40 MHz
100 MHz–300 MHz
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66 MHz–150 MHz
25 MHz–133 MHz
100 MHz–250 MHz
32 MHz–100 MHz
50 MHz–125 MHz
25 MHz–50 MHz
64 MHz–160 MHz
25 MHz–75 MHz
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