4/ (FOLSVH3OXV 'DWD 6KHHW 5HY $
LVTTL
LVCMOS2
GTL+
PCI
SSTL2
SSTL3
,15()
90,1 90$; 90,1
n/a n/a -0.3
n/a n/a -0.3
0.88 1.12 -0.3
n/a n/a -0.3
1.15 1.35 -0.3
1.3 1.7 -0.3
7DEOH '& ,QSXW DQG 2XWSXW /HYHOVD
9,/
90$;
0.8
0.7
INREF - 0.2
0.3 x VCCIO
INREF - 0.18
INREF - 0.2
9,+
90,1
90$;
2.0
VCCIO + 0.3
1.7
VCCIO + 0.3
INREF + 0.2 VCCIO + 0.3
0.5 x VCCIO VCCIO + 0.5
INREF + 0.18 VCCIO + 0.3
INREF + 0.2 VCCIO + 0.3
92/
90$;
0.4
0.7
0.6
0.1 x VCCIO
0.74
1.10
92+
90,1
2.4
,2/ ,2+
P$ P$
2.0 -2.0
1.7
2.0 -2.0
n/a
40 n/a
0.9 x VCCIO 1.5 -0.5
1.76
7.6 -7.6
1.90
8 -8
D The data provided in 7DEOH are JEDEC and PCI Specifications. QuickLogic devices either meet or exceed these
requirements. See preceding 7DEOH through 7DEOH and )LJXUH through )LJXUH for data specific to Quick-
Logic I/Os.
NOTE: All CLK and IOCTRL pins are clamped to the VCC rail, not the VCCIO. Therefore, these pins
can only be driven up to VCC + 0.3 V.
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