S9418 View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
S9418
Summit Microelectronics
'S9418' PDF : 10 Pages View PDF
S9418
PINOUT and SIGNAL DEFINITION
20-Pin PDIP
or 20-Pin SOIC
VREFH1 1
20 VREFH2
VREFH0 2
19 VREFH3
VDD 3
18 VOUT0
RDY/BSY# 4
17 VOUT1
CLK 5
16 VOUT2
CS# 6
15 VOUT3
DI 7
14 VREFL3
DO 8
13 VREFL2
MUTE 9
12 VREFL1
GND 10 11 VREFL0
2023 T PCon 2.0
Pin
1, 2
19, 20
3
4
Name
VREFH
VDD
RDY/
BSY#
5 CLK
6 CS#
7 DI
8 DO
9 MUTE
10 GND
11, 12 VREFL
13, 14
15, 16 VOUT
17, 18
Function
Vreference High:
VREFH - VDD > VREFL
Power Supply Voltage
Ready/Busy#: open drain output
indicating status of nonvolatile
write operations
Clock Input Pin: used for serial
data communication
Chip Select: When high deselects
the device and places it in a low
power mode
Data Input: serial data input pin
Data Output: serial data output pin
When active forces VOUT to VREFL
Power Supply Ground
Vreference Low
DAC Output: buffered D to A
converter output
The analog outputs of the S9418 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256th of the voltage differential between VREFH and
VREFL of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9418 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the VREFL and VREFH
inputs sets the full-scale output voltage for its respective
DAC. VREFL must be equal to or greater than ground
(positive voltage). VREFH must be greater (more positive)
than VREFL or equal to VDD.
Output Buffer Amplifiers
The voltage outputs are from precision unity-gain follow-
ers that can slew up to 1V/µs. The outputs can swing from
VREFL to VREFH. With a 0V to 5V output transition the
amplifier outputs typically settle to 1LSB in 40µs.
DIGITAL INTERFACE
The S9418 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS#), Data
input (DI) and Data output (DO). Data is clocked into the
device on the clock’s rising edge and out of the device on
the clock’s falling edge. Data is shifted in and out MSB first.
DO only becomes active after the device has been se-
lected and after a valid read command and address has
been received.
All data transfers are initiated after CS# goes low and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
2023 2.2 8/2/00
2
Share Link: 