S9418 View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
S9418
Summit Microelectronics
'S9418' PDF : 10 Pages View PDF
S9418
CS#
CLK
DI
DO
RDY/BSY#
S
T
C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A
R
T
Hi Z
(Pulled up to VDD)
VOUT
FIGURE 2. WRITE SEQUENCE
Rising Edge Sets
NV Write Enable Latch
CS#
CLK
2023 T fig02 2.0
Rising Edge Starts
NV Write
DI
C1 C0 A1
D0
Address and Data
are Don’t Care
C1 C0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
NV Write Enable
Latch is Reset
RDY/BSY#
e
FIGURE 3. NONVOLATILE WRITE SEQUENCE
2023 T fig03 2.0
NONVOLATILE WRITE
A nonvolatile write is a two step operation: it is initiated by
taking CS# low and clocking in a start bit followed by the
NV Write Enable command. At this point the host can take
CS# back high or continue clocking in data. This data is
don’t care and will be ignored by the S9418.
Next, the host takes CS# low again and issues a write
command and address and then clocks in the eight data
bits to be programmed. The host will then bring CS# high
and the data will be latched into the data register and a
nonvolatile write operation will commence.
The status of the nonvolatile write can be monitored on the
RDY/BSY# pin. A logic low indicates the write is still in
progress and the S9418 will not be accessible to the host;
a logic high indicates the write has completed and the
S9418 is ready for the next command. Refer to Figure 3
for an illustration of the sequence of bus conditions for a
nonvolatile write operation.
2023 2.2 8/2/00
4
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