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SBPH400-3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
SBPH400-3
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'SBPH400-3' PDF : 43 Pages View PDF
SBPH400-3
In the event of a packet reception during status transfer, the SBPH400 prematurely ends the
transfer by removing the status indication on the CTL[0:1]. Note that any status bits transferred
will be reset, even if the status transfer is prematurely terminated (i.e. if it is terminated after
the transfer of S[0:1], then S[0:1] will be reset. If it is terminated after the transfer of S[0:n]
where n>=3, then S[0:3] will be reset. The status transfer will be retried at the next available
opportunity if it was a 16 bit status transfer, or if it was a 4 bit status transfer and at least one
of the four status bits S[0] to S[3] is (still) 1.
2.8.8 Transmit
The link device requests access to the serial bus through LREQ when it wants to transmit
information. The SBPH400 arbitrates, using the timing algorithm appropriate to the request
type, to gain access to the serial bus. After the SBPH400 wins the arbitration, it grants the bus
to the link device by asserting grant on the CTL pins for one clock cycle, followed by idle for
one clock cycle. When it receives control of the bus, the link may assert one cycle of idle on
the CTL pins (this may be advisable when using PHY-Link isolation). While preparing data, the
link device keeps the ownership of the bus by asserting hold on the CTL pins. It is not
necessary for the link device to assert hold if it is ready to transmit as soon as bus is granted.
When it is ready to transmit a packet, the link device asserts transmit on the CTL pins along
with the first bits of the packet.
After sending the last bits of the packet when the link device does not wish to concatenate
another packet, the link device asserts idle on the CTL pins for two clock cycles before
tristating the CTL pins. After sending the last bits of the packet when the link device wishes to
concatenate another packet, the link device asserts hold on the CTL pins for one cycle,
together with the speed code for the next packet, followed by a single cycle of idle before
tristating the CTL pins. The link device may release the bus after the SBPH400 has asserted
grant by asserting idle on the CTL pins for three cycles, and may release the bus after
asserting hold by asserting idle on the CTL pins for two cycles.
The hold state indicates to the SBPH400 that the link device wants to send another packet
without releasing the bus (a concatenated packet). The SBPH400 responds to the hold by
waiting the required minimum time and then asserts transmit as before. The speed of the
concatenated packet is indicated at the time that the hold state is asserted, using the encoding
specified in Table 2.14.
Note that it is not permitted to transmit a S100 packet as a concatenated packet after
transmitting a higher speed packet. Note that, for compatibility with 1394-1995 PHYs, P1394a
requires that if “multi-speed concatenated packets” is not enabled (see Table 2.16), the speed
code for any concatenated packet which is received from the link will be ignored, and the
packet will be transmitted at the same speed as the packet to which it is concatenated. The
SBPH400 will supply the appropriate speed code as it transmits the packet on the bus.
When the link device has finished sending the last packet of the current bus ownership, it
releases the bus by asserting idle on the CTL pins for two consecutive clock cycles. The
transmit timing is shown in Figure 2.12.
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