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SBPH400-3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
SBPH400-3
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'SBPH400-3' PDF : 43 Pages View PDF
SBPH400-3
timing parameters are given in Table 2.21, and the signal relationships are illustrated in Figure
2.17 and Figure 2.18.
Table 2.21 PHY/Link interface reset and disable timing parameters
Symbol
Parameter
Unit
Min
TLPS_RESET Time for SBPH400 to recognize LPS logically
µs
1.2
deasserted and reset the interface
TLPS_DIS
Time for SBPH400 to recognize LPS logically µs
25
deasserted and disable the interface
TRESTORE Time to permit the optional differentiator and
µs
15
isolation circuits to restore during an interface
reset
Typ Max
2.75
30
20
Figure 2.17 PHY-Link reset timing
SCLK
LPS
TLPS_RESET TRESTORE
LPS
(isolated)
DATA
CTL
LREQ
Figure 2.18 PHY-Link disable timing
SCLK
LPS
TLPS_DISABLE TRESTORE
LPS
(isolated)
DATA
CTL
LREQ
31/43
2
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