SBPH400-3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'SBPH400-3' PDF : 43 Pages View PDF
SBPH400-3
Table 5.2 AC characteristics (digital interfaces)
Symbol Parameter
Measured Condition Unit Min Typ Max
tpsu
D, CTL, LREQ input setup to SCLK 50% to 50%
output
ns 6
tph
D, CTL, LREQ hold from SCLK output 50% to 50%
tlsu
D, CTL output setup to SCLK
50% to 50%
tlh
D, CTL output hold from SCLK
50% to 50%
td1
Delay time, SCLK input high to initial 50% to 50%
instances of D, CTL and LREQ
outputs valid
ns 0
ns 6.5
ns 0.5
ns 1
10
td2
Delay time, SCLK input high to
50% to 50%
subsequent instances of D, CTL and
LREQ outputs valid
ns 1
10
td3
Delay time, SCLK input high to D, CTL 50% to 50%
and LREQ outputs invalid (tri-state)
ns 1
10
Table 5.3 Clock and reset parameters
Symbol Parameter
Fextclk External clock Frequency
Dextclk External clock duty cycle
Jextclk External clock Jitter peak to peak
FSCLK
DSCLK
SCLK frequency
SCLK duty cycle
Power-on reset time, RESET# input
Measured Condition Unit Min Typ Max
24.576 MHz +/- 2.45 KHz
50% to 50%
45%
55%
100 pS peak to peak
50% to 50%
Fextclk × 2
50% to 50%
45%
55%
ms 2
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