SBPH400-3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'SBPH400-3' PDF : 43 Pages View PDF
SBPH400-3
3 Pin Description
Table 3.1 Pin description - normal operation
Pin name Pin number I/O Description
AGND
15, 23, 25, 80
Analog Ground
AVDD
6, 24, 26, 79
Analog Supply Voltage
CLK24
38
I External 24.576 MHz oscillator input (optional, see QX0)
CMC
CPS
64
I Configuration Manager Contender. Used to initialize the C register
at power-on reset. It should be programmed by connecting it to
VDD (C=1) or GND (C=0).
78
I Cable power status.
CTL[0:1]
46, 45
I/O Control signals for PHY-Link interface
D[0:7]
59 - 51
I/O Data signals for PHY-Link interface
DGND
12, 13, 14, 27,
28, 29, 30, 31,
34, 40, 43, 48,
49, 50, 61, 69,
70, 72, 73, 74
Digital Ground
DVDD
32, 33, 47, 71
Digital Supply Voltage
ISO
LACT
68
I Link interface isolation logic control. Logic level 1 on this pin
enables the isolation logic, 0 disables the isolation logic (normally
tied to VDD or GND as required)
41
I Link Active. Used to initialize the Link Active register on power
reset. It should be programmed by connecting it to VDD (Link Active
= 1) or GND (Link Active = 0).
LKON
42
O Link on o/p
LPS
62
I Link power status.
LREQ
44
I Link request to SBPH400
N/C
35, 75, 76
I Inputs not used in normal operation, may be connected to VDD or
GND, or left unconnected.
OGND
37
I Oscillator ground
OVDD
39
I Oscillator supply voltage
PC[0:2]
65 - 67
I Power Class input
PDISABLE
63
I Ports disable. Used to initialize all three ports as disabled on
power-on reset.
QX0
38
I 24.508 MHz crystal input 0 (optional, see CLK24)
QX1
36
I 24.508 MHz crystal input 1 (optional, left unconnected if not used,
must not be taken to power or GND)
R[0:1]
22, 21
External resistor for bias current setting
RESET#
77
I Reset. Taking this signal low causes all activity to cease. When this
signal is taken high, all appropriate registers and outputs are
initialized to their power reset values and a 166µsec bus reset is
initiated.
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