SC486EVB View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC486EVB' PDF : 26 Pages View PDF
SC486
POWER MANAGEMENT
Design Procedure (Cont.)
For our DDR2 VDDQ example:
IRIPPLE_VBAT(MIN) = 2.62AP-P and IRIPPLE_VBAT(MAX) = 3.28AP-P
From this we can calculate the minimum inductor
current rating for normal operation:
I = I + I 2 A INDUCTOR(MIN)
OUT(MAX )
RIPPLE _ VBAT(MAX )
(MIN)
For our DDR2 VDDQ example:
R
ESR_TR(MAX)
=
5.5mΩ
for
a
full
10A
load
transient
We will select a value of 7.5mΩ maximum for our
design, which would be achieved by using two 15mΩ
output capacitors in parallel.
Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:
RESR(MIN)
=
2•
3
π • COUT
•
fSW
IINDUCTOR(MIN) = 11.6A(MIN)
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (RESR_ST(MAX)) and transient ESR
(RESR_TR(MAX)):
( ) R = ESR _ ST(MAX)
ERRST − ERRDC • 2 Ohms
IRIPPLE _ VBAT(MAX )
This criteria should be checked once the output
capacitance has been determined.
Now that we know the output ESR we can calculate the
output ripple voltage:
V = R • I V RIPPLE _ VBAT(MAX)
ESR RIPPLE _ VBAT(MAX) P−P
and
V = R • I V RIPPLE_ VBAT(MIN)
ESR RIPPLE _ VBAT(MIN) P−P
Where ERRST is the static output tolerance and ERRDC is
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1%
feedback resistors.
For our DDR2 VDDQ example:
ERRST = 72mV and ERRDC = 36mV, therefore
RESR_ST(MAX) = 22mΩ
( ) RESR _ TR(MAX)
=
ERRTR − ERRDC
IOUT
+
IRIPPLE _ VBAT(MAX )
2
Ohms
Where ERRTR is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the IOUT
term by 2.
For our DDR2 VDDQ example:
V
= 25mV and V
= 20mV
RIPPLE_VBAT(MAX)
P-P
RIPPLE_VBAT(MIN)
P-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, V , should be approximately 15mV at minimum
FB
P-P
VBAT, and worst case no smaller than 10mVP-P. If
VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component
values should be revisited in order to improve this. A small
capacitor, C , may be required in parallel with the top
TOP
feedback resistor, RTOP, in order to ensure that VFB is large
enough. CTOP should not be greater than 100pF. The value
of C can be calculated as follows, where R is the
TOP
BOT
bottom feedback resistor. Firstly calculating the value of
ZTOP required:
( ) ZTOP
=
RBOT
0.015
•
VRIPPLE _ VBAT(MIN)
− 0.015
Ohms
For our DDR2 VDDQ example:
ERRTR = 100mV and ERRDC = 36mV, therefore
2006 Semtech Corp.
16
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