SC486EVB View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC486EVB' PDF : 26 Pages View PDF
SC486
POWER MANAGEMENT
Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star
connection at the thermal pad, which in turn is connected using 4 vias to the ground plane. All components that are
referenced to VSSA should connect to it directly on the chip side, and not through the ground plane.
VDDQ: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace in a quiet layer if possible from the output capacitor back to the chip.
Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA and VSSA, VDDP and
PGND1) and connected directly to them on the same side.
VTT: output capacitors should be located right across the VTT output pins (VTT and PGND2) as close as possible to
the part to minimize parasitics.
The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections). Power components should be placed to minimize loops and
reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not
use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most
critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must
always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC486 DDR2 reference design used in the Design Procedure section while explaining the layout
guidelines in more detail.
VBAT 5VSUS 5VRUN
VDDQ
R4 10R
C2
C1
R5 4k64
1u
no-pop
REF
R8
23k2
R6
10R
C9
1u
VTT
VDDQ
R7 10R
C3
no-pop
R9 0R
C10
no-pop
C15
10u
C16
10u
R1
715k
R2
10R
U1
11 VTTEN
3 VDDQS
2 TON
6 FB
8 REF
9 COMP
C11
1n
C12
1u
C17
1u
10 VTTS
5 VCCA
4 VSSA
14
15
VTT
VTT
12
13
VTTIN
VTTIN
16
17
PGND2
PGND2
5VSUS
SC486
PGD 7
EN/PSV 1
R3 470k
D1
VBAT
PGOOD
BST 24
DH 23
ILIM 21
LX 22
R10 13k0
C4
0.1uF
DL 19
VDDP 20
PGND1 18
C18
1u
Q1
IRF7811AV
Q2
FDS6676S
C5
2n2/50V
C6
0u1/25V
C7
10u/25V
C8
10u/25V
L1 1u5
+ C13
220u/15m
VDDQ
+ C14
220u/15m
Figure 4: DDR2 Reference Design and Layout Example
Sample DDR2 Design Using SC486
VBAT = 9V to 19.2V
VDDQ = 1.8V @ (8+2)A
VTT = 0.9V @ 2A
2006 Semtech Corp.
19
www.semtech.com
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