SC908 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC908' PDF : 30 Pages View PDF
SC908
Applications Information (continued)
VREF power supply rejection with respect to VAD will be
similar.
improving overall load transient response, and may also
improve input supply rejection.
The VREF pin is a high impedance source. Any load on
VREF will degrade LDO and switching regulator voltage
accuracy. Note that the 10MΩ impedance of a typical
oscilloscope probe is not large enough to prevent loading
of the VREF pin.
LDO Power Supply Rejection
Power supply rejection must be considered with respect
to two inputs. The buffered bandgap reference is powered
by the greater of two possible sources, V (an internal/
VSYS
external supply voltage, derived from VAD when present)
and V . The LDO is powered from the LVIN pin. PSRR is
BAT
L
defined as the power supply rejection from LVIN to LVOUT
with the reference and reference buffer powered from BAT
as DC voltage. The reference voltage VREF power supply
rejection specification (PSRR ) is with respect to BAT. Any
REF
reference voltage power supply noise or ripple is seen in
the LDO as noise on the LFB reference voltage. This noise
is then gained-up to the output by the reciprocal of the
LFB divider network, or by the gain (1 + RL1/RL2).
In the special case V = V (the LVIN pin is connected
LVIN
BAT
directly to the battery), the power supply rejection of the
LDO, PSRR , is determined by
LBAT
PSRRLBAT
20 log10¨¨©§¨¨©§1
RL1
RL2
¸¸¹· u10PSRRREF
20
PSRRL
10
20
¸¸¹·
LDO Current Limit and Short-Circuit Protection
The LDO regulator has current limit circuitry to ensure that
the output current will not damage the device during
output short-circuit to ground, overload, or start-up. The
current limit is guaranteed to be greater than 200mA to
allow fast charging of the output capacitor and for high
transient load currents.
LDO Input and Output Capacitor
A minimum LDO input and output capacitance of 1μF
with a maximum equivalent series resistance (ESR) of less
than 1Ω over temperature is recommended. Increasing
the output capacitance will further reduce output noise
and improve load transient response. A larger input
capacitor will reduce input droop due to load transients,
Switching Regulator
The SC908 contains a synchronous step-down Pulse Width
Modulated (PWM), DC-DC converter (also referred to as a
Buck Converter or Switcher) with integrated power
devices. The switching frequency is set nominally to
1MHz, allowing the use of small inductors and capacitors.
The current limit of the internal PMOS switch (I ), allows
LIM_P
a DC output current of at least 150mA with appropriate
external components. For maximum efficiency over the
full load range, the switcher will automatically operate in
Power Save (PSAVE) mode with light loads, and in PWM
(normal switching) mode for heavier loads.
The voltage feedback loop uses an external feedback
divider. An internal synchronous NMOS low side switch is
used. An external Schottky diode on the LX pin is not
required.
Switcher Programmable Output Voltage
The buck converter regulates its output to obtain 0.5V at
the SFB pin. The output can be programmed to any
voltage from 1.0V to 3.0V by an external resistor divider
network from the external circuit node SVOUT to the SFB
pin. The equation for setting the output voltage is
969287
96)%
56
56
SFB is a high impedance input, therefore the magnitude
of resistances used will be determined by a trade off
between feedback network current and product design
practice. A 25pF feedback capacitor, designated C , is
SFB
required for stability in PWM mode.
When considering the effect of buck converter load
current on performance specifications, the current flowing
in the feedback divider network should be included in the
load. In most situations, PSAVE mode operation will
require a capacitor from SFB to AGND. Refer to the PSAVE
mode description.
Switcher Power Save (PSAVE) Mode Operation
The PSAVE mode is automatically activated or deactivated
with light to heavy loads, maximizing efficiency across the
25
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