SC908 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC908' PDF : 30 Pages View PDF
SC908
Applications Information (continued)
full load range. The SC908 automatically detects the load
current at which it should enter PSAVE mode. This detec-
tion is based on the minimum peak current in the PMOS
high side switch in PWM mode. This will vary with input
voltage, output voltage, and the converter external
inductance (L ). PSAVE entry DC load current will decrease
S
with decreasing L .
S
In a PSAVE mode burst cycle, V rises from a lower to
SVOUT
an upper voltage threshold with a switching burst (see
Figure 3). Within the burst, the PMOS switch is turned on
until the PMOS current reaches a current limit. It is then
turned off for a fixed duration, and then turned on again
(cycle may be repeated). The low-side NMOS switch is
turned on whenever the high-side switch is off. When the
upper threshold (1.5% above the programmed regulation
voltage) is reached, the switching burst is halted. This
reduces the quiescent current by turning off both high-
side and low-side switches. V decays to the lower
SVOUT
threshold (0.8% above the programmed regulation
voltage) due to the load current discharging the output
capacitor, which initiates another switching burst. The
burst-time to off-time ratio in PSAVE will decrease with
decreasing load current.
PSAVE Mode at
Moderate Load
Higher Load
Applied
BURST
OFF
BURST OFF
+1.6%
+0.8%
VS VOUT
Prog’d
Voltage
PSAVE Mode at
High Load
BURST
PWM Mode at
High Load
PWM Mode
lope frequency will exceed 20kHz for any load greater
than 3mA, if external component recommendations have
been followed. The envelope minimum frequency will
decrease with increasing C capacitance.
SVOUT
The SC908 automatically detects when to exit PSAVE
mode by monitoring V , and thus V . If the switching
SFB
SVOUT
burst output current is insufficient to supply the output
load, V will not rise to the upper threshold during a
SVOUT
switching burst, but will instead decrease. If V droops
SVOUT
to 2% below the programmed regulation voltage, PSAVE
mode will be deactivated, and the buck converter will
revert immediately to PWM mode. To prevent rapid PWM/
PSAVE mode cycling, the PSAVE entry and exit criteria are
chosen to provide load hysteresis. After reverting to PWM
mode the switcher will remain in PWM mode for 128
switching cycles (approximately 128μs) before it is permit-
ted to re-enter PSAVE mode.
Proper operation of PSAVE mode requires the addition of
a capacitor from the SFB pin to ground, designated C , of
SFG
value
C =C ×R /R .
SFG
SFB
S1 S2
Switcher Efficiency
Switcher efficiency is affected by input voltage, output
voltage, temperature, and choice of inductor. It also varies
with load, and on which mode, PWM or PSAVE, is active.
The mode selection depends not only on the instanta-
neous load, but also on the immediate past load, since
transitions between PSAVE and PWM modes are load
dependent, with hysteresis.
-2%
Inductor
Current
0A
Time
Figure 3 Power Save Operation
The PSAVE switching burst is designed so that the induc-
tor current ripple is similar to that of PWM mode. To
prevent audible noise, the PSAVE mode parameters have
been chosen such that the minimum PSAVE burst enve-
For high loads (those that unconditionally place the
switcher in PWM mode), the efficiency typically exceeds
90%. For low loads (those that unconditionally place the
switcher in PSAVE mode), efficiency can vary from 88 to
92% over all conditions. As the load decreases further, the
SC908 quiescent current eventually becomes significant,
and efficiency drops off sharply.
At intermediate modes, the switcher could select either
PSAVE or PWM mode depending on whether the recent
past load was higher or lower, due to load hysteresis.
Within the hysteresis load range, efficiency can vary from
86% to 92%, over all conditions.
26
Share Link: 
