SML2108
PRELIMINARY
S
T
S
A
T
Master
R
T
Device R/
Address W
Location Address
O
P
SDA
1 0 0 1x x x 0
0 0 0 00 1 0 0
DDDDDDDD
76543210
Slave
A
A
A
C
C
C
K
K
K 2053 Fig17
Figure 17. 8-Bit DAC Volatile Register Write
S
T
A
Master
R
T
Device R/
Address W
Location Address
SDA
1 0 0 1x x x 0 0 0 0 00 1 0 0
S
T
A
R
Device R/
T
Address W
1 0 0 1x x x 1
NS
AT
C
K
O
P
DDDDDDDD
76543210
Slave
A
A
C
C
K
K
A
C
2053 Fig18
K
Figure 18. 8-Bit DAC Volatile Register Read with Dummy Write
S
T
S
A
T
Master
R
T
Device R/
Address W
Location Address
O
P
SDA
1 0 0 1x x x 0
0 0 0 00 1 1 0
DDDDDDDD
76543210
Slave
A
A
A
C
C
C
K
K
K 2053 Fig19
Figure 19. 8-Bit DAC Non-volatile Register Write
S
T
A
Master
R
T
Device R/
Address W
Location Address
SDA
1 0 0 1x x x 0 0 0 0 00 1 1 0
S
T
A
R
Device R/
T
Address W
1 0 0 1x x x 1
NS
AT
C
K
O
P
DDDDDDDD
76543210
Slave
A
A
C
C
K
K
A
C
2053 Fig20
K
Figure 20. 8-Bit DAC Non-volatile Register Read with Dummy Write
SUMMIT MICROELECTRONICS, Inc.
2053 2.2 11/07/00
17