SN260 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'SN260' PDF : 88 Pages View PDF
SN260
5.8
Functional description
Reset detection
The SN260 contains multiple reset sources. The reset event is logged into the reset source
register, which lets the CPU determine the cause of the last reset. The following reset
causes are detected:
● Power-on-reset
● Watchdog
● PC rollover
● Software reset
● Core power dip
5.9
Power-on-reset (POR)
Each voltage domain (1.8V digital core supply VDD_CORE and pads supply VDD_PADS)
has a power-on-reset (POR) cell.
The VDD_PADS POR cell holds the always-powered high-voltage domain in reset until the
following conditions have been met:
● The high-voltage pads supply VDD_PADS voltage rises above a threshold.
● The internal RC clock starts and generates three clock pulses.
● The 1.8V POR cell holds the main digital core in reset until the regulator output voltage
rises above a threshold.
Additionally, the digital domain counts 1,024 clock edges on the 24MHz crystal before
releasing the reset to the main digital core.
Table 11 lists the features of the SN260 POR circuitry.
Table 11. POR specifications
Parameter
VDD_PADS POR release
VDD_PADS POR assert
1.8V POR release
1.8V POR hysteresis
Min.
1.0
0.5
1.35
0.08
Typ.
Max.
Unit
1.2
1.4
V
0.6
0.7
V
1.5
1.65
V
0.1
0.12
V
5.10
5.10.1
Clock sources
The SN260 integrates two oscillators: a high-frequency 24MHz crystal oscillator and a low-
frequency internal 10kHz RC oscillator.
High-frequency crystal oscillator
The integrated high-frequency crystal oscillator requires an external 24MHz crystal with an
accuracy of ±40ppm. Based upon the application bill of materials and current consumption
requirements, the external crystal can cover a range of ESR requirements. For a lower ESR,
the cost of the crystal increases but the overall current consumption decreases. Likewise, for
higher ESR, the cost decreases but the current consumption increases. Therefore, the
designer can choose a crystal to fit the needs of the application.
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